With the proliferation of data networks, the demands on network devices which receive and transmit data traffic are evolving. In many such networks, these devices (e.g., switches or routers) are being called on to switch a rapidly increasing amount of traffic. Moreover, as transmission speeds increase, network devices must switch the data traffic at a faster rate to keep up with the inflow. One factor driving these changes is the increase in multicast traffic. Multicast messages are commonly used for one-to-many delivery of data.
When a network device receives a data packet, it typically stores the packet temporarily in the device Random Access Memory (RAM) while a determination is made regarding the forwarding decision. Network devices often have a large number of egress ports, and multicast data packets received by a device may be directed to a significant subset of those ports. Thus, in many circumstances, multicast packets are read more than once from a single bank of memory as the packet is copied for each port through which it is forwarded. As the number of ports on a network device increases, memory bandwidth requirements also increase and may eventually exceed the bandwidth available from a single memory device. Therefore, there is a need in the art for a network device with a memory architecture that scales with increasing demand for bandwidth.